1. Field of the Invention
The present invention relates generally to image sensors, and more particularly, to a pixel circuit coupled to a reset control signal node of another pixel circuit for receiving a reset voltage and/or a power supply voltage, to reduce wiring in an image sensor.
2. Description of the Related Art
CMOS (complementary metal oxide semiconductor) image sensors are commonly included in many electronic devices such as mobile phones and digital still cameras. A CMOS image sensor senses an image, converts the image into electrical signals that are in turn converted into digital image signals. The digital image signals output from the CMOS image sensor are typically for three-colors (red, green, and blue). After being processed, the digital image signals drive a display device such as a liquid crystal display (LCD).
FIG. 1 shows a block diagram of a conventional CMOS image sensor 100. Referring to FIG. 1, the image sensor 100 includes an APS (active pixel sensor) array 110, a row driver 120, and an ADC (analog-to-digital converter) 130.
The row driver 120 receives a control signal from a row decoder (not shown), and the ADC 130 receives a control signal from a column decoder (not shown). The image sensor 100 also includes a controller (not shown) that generates timing control signals as well as addressing signals used for detecting and outputting a respective image signal for each pixel.
FIG. 2 illustrates an example color filter pattern of the APS array 110 of FIG. 1. The CMOS image sensor 100 that is a color image sensor includes a respective color filter in an upper part of each pixel to receive and detect light of a certain color. The CMOS image sensor 100 includes at least three types of color filters to form a color signal. The most common color filter pattern is a Bayer pattern as illustrated in FIG. 2.
In FIG. 2, a pixel with a “G” designation has a color filter for the green color, a pixel with an “R” designation has a color filter for the red color, and a pixel with a “B” designation has a color filter for the blue color. In such a Bayer pattern, green, which is closely related to a luminance signal, is placed in all rows, and red and blue are placed in alternate rows to enhance luminance resolution. For enhanced resolution, a CMOS image sensor typically includes more than one million pixels for implementing common electronic devices such as a digital still camera.
The APS array 110 includes photodiodes which convert received light of such colors into electrical signals to generate image signals. The analog image signals output from the APS array 110 are three-color (red, green, and blue) analog image signals. The ADC 130 receives the analog image signals and converts the analog image signals into digital signals using a well-known correlated double sampling (CDS) method.
FIG. 3 shows a circuit diagram of a unit pixel circuit 300 included in the APS array 110 of FIG. 1 for a respective pixel. Referring to FIG. 3, the unit pixel circuit 300 includes a photodiode PD and four transistors. In analog to digital conversion using the CDS method, a reset signal VRES and an image signal VSIG are output from the pixel circuit 300 for each pixel.
To this end, referring to FIG. 3, a row for the pixel is selected by activation of a row select signal SEL. For output of the reset signal VRES, a reset control signal RX turns on a reset transistor to couple a power supply voltage VDD to a floating diffusion (FD) node. Such power supply voltage VDD coupled to the FD node forms the reset signal VRES output through a source follower transistor and a row select transistor.
For output of the image signal VSIG, the photodiode PD converts received light into an electrical signal that is transferred to the FD node via a transfer transistor upon activation of a transfer control signal TX. Such electrical signal at the FD node is output as the image signal VSIG through the source follower transistor and the row select transistor.
For correlated double sampling, the difference between the reset signal VRES and the image signal VSIG, which is an analog signal, is converted into a digital signal by the ADC 120. The row select signal SEL, the reset control signal RX, and the transfer control signal TX may be generated by the row driver 120 in FIG. 1.
As illustrated in FIG. 3, the unit pixel circuit 300 in the CMOS image sensor 100 includes the photodiode PD and the transistors for outputting the reset signal VRES and the image signal VSIG with appropriate timing.
Recently, the number of pixels desired in an image sensor has increased such that smaller size pixels are in turn desired. Therefore, metal wiring for connecting the photodiode PD and the transistors in the unit pixel circuit 300 is desired to be reduced for securing sufficient space for the photodiode PD.
To this end, the number of transistors used in a unit pixel circuit may be reduced as disclosed in U.S. Pat. No. 6,710,803 to Kang for example. Alternatively, size of the transistors in the unit pixel circuit 300 may be reduced using advanced fabrication technology. However, there is a limit to reducing the number of transistors required in the unit pixel circuit 300, and advanced fabrication technology is expensive.
To ensure that external light reaches the photodiode PD, metal wiring in an upper layer of the photodiode PD, which may be a major obstruction for such light, may be minimized. However, there is a limit to reducing the widths of metal wires when complying with design rules in integrated circuit fabrication.